发明名称 |
Data processing method, precoding method, and communication device |
摘要 |
An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s1 and a second complex signal s2 with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s1, and Y indicates the number of bits used to generate the second complex signal s2. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved. |
申请公布号 |
US9479234(B2) |
申请公布日期 |
2016.10.25 |
申请号 |
US201514859737 |
申请日期 |
2015.09.21 |
申请人 |
SUN PATENT TRUST |
发明人 |
Murakami Yutaka;Kimura Tomohiro;Ouchi Mikihiro |
分类号 |
H04B7/02;H04B7/04;H03M13/25;H04L1/00;H04L1/08 |
主分类号 |
H04B7/02 |
代理机构 |
Wenderoth, Lind & Ponack, L.L.P. |
代理人 |
Wenderoth, Lind & Ponack, L.L.P. |
主权项 |
1. A transmission signal generation device, comprising:
an encoder configured to generate a first bit sequence that is an N-bit codeword from a K-bit information bit sequence, where K and N are each an integer greater than or equal to 1; a bit adjuster configured to (i) judge whether or not to add a known bit sequence to the first bit sequence, and (ii) when judging negatively, output the first bit sequence, and when judging affirmatively, output a second bit sequence that is obtained by adding the known bit sequence to the first bit sequence; and a mapper configured to modulate the first bit sequence of N bits or the second bit sequence using a modulation scheme selected from among a plurality of modulation schemes, wherein a modulation symbol of the selected modulation scheme has X bits, where X is an integer greater than or equal to 1, when N is an integral multiple of X, the bit adjuster does not add the known bit, and when N is not the integral multiple of X, the bit adjuster adds the known bit of α×X−N bits to the first bit sequence, where α and α×X−N are each an integer greater than or equal to 1. |
地址 |
New York NY US |