Method for controlling an integrated circuit

摘要

A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

主权项

1. A method for controlling an integrated circuit, said method comprising providing an integrated circuit that comprises logic cells, a clock-tree cell, and a semiconductor substrate, wherein said logic cells each comprise at least a first field-effect transistor and a second field-effect transistor, wherein said first field-effect transistor is a pMOS transistor, wherein said second field-effect transistor is an nMOS transistor, wherein said clock-tree cell comprises at least a third field-effect transistor and a fourth field-effect transistor, wherein said third field-effect transistor is a pMOS transistor, wherein said fourth field-effect transistor is an nMOS transistor, wherein said clock tree cell is configured to provide a clock signal to said logic cells, wherein said logic cells and said clock-tree cell are formed on said semiconductor substrate, wherein each of said field-effect transistors comprises a source, a drain, a conduction channel region, a gate stack, and a back gate, wherein said gate stack is disposed above said conduction channel region, wherein said back gate is disposed facing said gate stack on an opposite side of said conduction channel, and wherein a back gate potential difference of one of said field-effect transistors is defined as a difference between an electric potential applied to said source of said field-effect transistor less an electric potential applied to said back gate of said field-effect transistor, when said field-effect transistor is a pMOS transistor, and an electric potential applied to said back gate of said field-effect transistor less an electric potential applied to said source of said field-effect transistor, when said field-effect transistor is an nMOS transistor, said method further comprising applying a first back gate electric potential difference to a first field-effect transistor of a logic cell, applying a second back gate electric potential difference to a second field-effect transistor of said logic cell, and only one of applying a third back gate electric potential difference to said third field-effect transistor, wherein said third back gate potential difference is positive, wherein said third back gate potential difference has a value that is greater than said first back gate potential difference applied, which is applied concurrently, and applying a fourth back gate electric potential difference to said fourth field-effect transistor, wherein said fourth back gate potential difference is positive, wherein said fourth back gate potential difference has a value that is greater than said second back gate potential difference that is applied concurrently.