| 摘要 |
The present disclosure relates to a circuit structure for enhancing EFT immunity of primary side converter, including a power ground and a feedback voltage detecting block, a feedback current detecting block, a controller, a PWM driving block, a high voltage starting block, a starting unit, a circuit for enhancing EFT immunity of primary side converter, a power MOS transistor, and an OR gate configured to perform a logical OR of an off-time calculated theoretically and an off-time output by an off-time control block. The present disclosure enhances EFT immunity effectively and improves the dynamic characteristics of the primary side converter. |
| 主权项 |
1. A circuit structure for enhancing EFT immunity of primary side converter, comprising:
a power ground and a feedback voltage detecting block (103), a feedback current detecting block (106), a controller (104), a PWM driving block (105), a HV start-up block (102), a start-up unit (107), a circuit for enhancing EFT immunity of primary side converter, a power MOS transistor (109), and an OR gate (108) configured to perform a logical operation OR of an off-time calculated theoretically and an off-time output by an off-time control block (203); wherein, the circuit for enhancing EFT immunity of primary side converter comprises a VSENSE abrupt change detecting block (201), the off-time control block (203), an OCP threshold value adjusting block (204) and a timing block (202); wherein, an input of the VSENSE abrupt change detecting block (201) is connected with a feedback voltage VSENSE terminal, outputs of the VSENSE abrupt change detecting block (201) are respectively connected with an input of the start-up unit (107), an input of the OCP threshold value adjusting block (204) and an input of the timing block (202); inputs of the off-time control block (203) are connected with outputs of the timing block (202), and an output of the off-time control block (203) is connected with an input of the OR gate (108); another input of the OCP threshold value adjusting block (204) is connected with an output of the controller (104), and an output of the OCP threshold value adjusting block (204) is connected with an input of the feedback current detecting block (106); an input of the feedback voltage detecting block (103) is connected with the VSENSE terminal, and an output of the feedback voltage detecting block (103) is connected with an input of the controller (104); outputs of the controller (104) are respectively connected with an input of the OCP threshold value adjusting block (204) and another input of the OR gate (108); an output of the OR gate (108) is connected with an input of the PWM driver (105); an output of the PWM driver (105) is connected with an input of the power MOS transistor (109); the drain of power MOS transistor (109) is connected with the HV start-up block (102) and a high voltage port SW; the source of power MOS transistor (109) is connected with the feedback current detecting block (106) and a current feedback port ISENSE; the feedback current detecting block (106) is also connected with the OCP threshold value adjusting block (204), and a current feedback port ISENSE; the high voltage starting block (102) is respectively connected with the high voltage port SW and a power port VDD. |
