Frequency division circuit

摘要

An odd number of inverting memory blocks are connected in series in a closed ring circuit. Each inverting elememt comprises a P channel field effect transistor and an N channel field effect transistor which are connected in parallel opposition. Control signals of the same phase are applied to the gate electrodes of the P and N channel field effect transistors. An inverter circuit comprising a pair of field effect transistors having gate electrodes is connected to one of two parallel connected, conductive electrodes of a temporary memory switching circuit. Control gate electrodes of the inverting memory block are controlled by control signals having the same phase and at a frequency to be divided for producing a frequency divided output from the output of one of the inverting memory blocks.