High speed sequential read method for flash memory

摘要

A flash memory device implements a sequential read method using overlapping read cycles to initiate the bit-line precharge and equalization operation for a next memory cell address prior to the completion of the read cycle of the current memory cell address. More specifically, the sequential read method implements overlapping read cycle where the bit-line precharge and equalization operation is started for a memory cell of the next address while the memory cell of the current address is being read out. In this manner, the read speed for the sequential read operation of the flash memory device is improved. In some embodiments, the memory cell array for each input-output (I/O) of the flash memory device is partitioned into two sub-banks to further reduce the read cycle time by enabling early activation of the word-line for the next sub-bank.

主权项

1. A method in a non-volatile memory device including an array of memory cells, the method for performing a sequential read operation from a plurality of memory cells having consecutive memory cell addresses, the method comprising:
detecting a first address transition relating to a first memory cell address at the start of a first read cycle; activating a first word-line associated with the first memory cell address; selecting a first bit-line associated with the first memory cell address; precharging the first bit-line and a first reference bit-line; equalizing the first bit-line and the first reference bit-line; after precharging and equalizing the first bit-line, enabling the sensing of the first bit-line during the first read cycle and detecting, during the first read cycle, a second address transition relating to a second memory cell address for a second read cycle, the second memory cell address being a next address following the first memory cell address; selecting, during the first read cycle, a second bit-line associated with the second memory cell address; precharging, during the first read cycle, the second bit-line and a second reference bit-line; equalizing, during the first read cycle, the second bit-line and the second reference bit-line; latching, at an end of the first read cycle, a first output data associated with the first memory cell address; and after precharging and equalizing the second bit-line, enabling the sensing of the second bit-line during the second read cycle.