发明名称 SETT ATT REGLERA DEN AV ETT VEXELSTROMSNET TILL EN FORBRUKARE AVGIVNA ELEKTRISKA EFFEKTEN OCH ANORDNING FOR ATT UTFORA SETTET
摘要 In regulating power by phase control, the deviations of the load current from the sinusoidal variation should be small and occur at a high frequency so that they can be suppressed by simple filters. For this purpose, the on time is controlled with high keying frequency over each half wave of the alternating mains voltage, in such a manner that the mean value of the switched current tracks a sinusoidal wave. A nominal sinusoidal voltage is generated by means of a first circuit arrangement (R5, R6, P2, R7, G2). An actual voltage is derived from a load current by means of a second circuit arrangement (R1, G3). A comparison circuit (V2) outputs an output signal when the actual voltage is greater than the nominal voltage. A pulse oscillator (10) outputs high-frequency square wave pulses to the set input of a flip flop (FF), the reset input of which is connected to the output of the comparison circuit. The output signal of the flip flop (FF) controls a semiconductor switch (T1) which is connected to one arm of a rectifier bridge (G1), the other arm of which is located in the load circuit. An output signal of the flip flop (FF), generated in the set state of the flip flop (FF), keeps the semi-conductor switch (T1) in its conducting state. <IMAGE>
申请公布号 SE7806333(A) 申请公布日期 1978.12.02
申请号 SE19780006333 申请日期 1978.05.31
申请人 POUL HAHN * EVERS 发明人 H-D * GRUDELBACH
分类号 G05F1/445;H02M5/257;(IPC1-7):G05F1/66 主分类号 G05F1/445
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