发明名称 TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL
摘要 Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.
申请公布号 US2016336432(A1) 申请公布日期 2016.11.17
申请号 US201615221641 申请日期 2016.07.28
申请人 United Silicon Carbide, Inc. 发明人 Bhalla Anup;Alexandrov Peter
分类号 H01L29/66;H01L21/02;H01L21/306;H01L29/808 主分类号 H01L29/66
代理机构 代理人
主权项 1. A method of fabricating a trench JFET from a substrate of a first doping type, the substrate comprising: a heavily doped backside drain region;a center medium doped drift region; anda topside heavily doped source region,the method comprising:etching trenches into the substrate from the topside to form mesas comprising drift region material and source region material;implanting dopant of a second doping type on the bottoms and sides of the trenches to form gate regions; andimplanting dopant of the first doping past the gate regions on the sides of the trenches and into the mesas.
地址 Monmouth Junction NJ US
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