| 摘要 |
PURPOSE:To improve an error detection rate by dividing the output of each semiconductor memory element into several groups and by leading respective groups to different parity check circuits. CONSTITUTION:This system is provided with semiconductor memory elements 1-1 and 1-2 with several bit outputs and parity ckeck circuits 3-1 and 3-2, and the outputs of elements 1-1 and 1-2 are divided into bits A0 to A7 of data A and bits B0 to B7 of data B; parity generator 2-1 generates check bit PA for data A, and parity generator 2-2 parity bit PB for data B. Then, elements 1-1 and 1-2 are applied at the same time with the same address information AD0 to the information AD5, chip select signal CS, and read/write signal R/W. Next, outputs of elements 1-1 and 1-2 classified by groups are supplied to different circuits 3-1 and 3-2, where comparison of parity bits is done, and an error signal is outputted. |
