| 摘要 |
PURPOSE:To ensure the high-quality transmission by combining the error correction encoding system in case the multilevel transmission system is applied to the circuit featuring a very low S/N ratio. CONSTITUTION:A conversion is given into the bipolar signal of the input at the transmission side, and the signal is written into transmission buffer memory BMS1 to be then divided. When frame clock F1 and check bit Ci are grown, the output signal of parallel-series converter P/S is supplied to error correction encoder ENCOD with check bit Ci inserted at frame position F1. After conversion into the parallel signal through series-parallel converter C/P, the subsequent processes are identical to the conventional ones. |
