发明名称 FAILURE DETECTION SYSTEM OF CONTROL MEMORY DEVICE
摘要 PURPOSE:To make the recovery of a control memory rapid by comparing an error micro instruction with the correct micro instruction corresponding to it bit by bit and displaying the result. CONSTITUTION:The micro instruction read from control memory 2 is checked in error check circuit; and when error is detected, the error micro instruction in read register 3 and the error address in address register 6 are saved to save register 5 and address register 7 respectively by circuit 4. Then, external memory 1 reads correct instruction corresponding to the error micro instruction into read register 8 on a basis of address 7. Next, the error micro instruction in register 5 and the correct instruction are compared bit by bit in comparison circuit (exclusive OR circuit) 9, and the error bit is displayed. Thus, it is possible to focus the range of the defective position of memory 2 easily and perform the recovery rapidly.
申请公布号 JPS54113221(A) 申请公布日期 1979.09.04
申请号 JP19780019787 申请日期 1978.02.24
申请人 HITACHI LTD 发明人 KUBOTA TADASHI
分类号 G06F11/08;G06F11/10;G06F12/16;G11C29/00 主分类号 G06F11/08
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