| 摘要 |
PURPOSE:To make the line lengths between the clock nets and the load gates equal to each other and to minimize the clock skew by forming a clock net for each area which is obtained by splitting the LSI circuit, by providing a clock driver to each clock net to feed a clock to the net and by making the floating capacitance of each clock net regulable. CONSTITUTION:The clock net 6 similar to the power net 5 is divided into three function blocks 2, the clock driver 7 is provided to each net to feed a clock from the outside to the net through the pad 8. In each block 2, the clock cell 9 is placed between both rows of the power blocks 4 and the base cells 3, a clock is fed to the required cell 3 through the cell 9 and the channels 61, 62. The net 6 is of Al wiring, the resistance can be disregarded, the delay times from the drivers 7 to the respective cells 9 are all the same and are determined by both the floating capacitance which the net 6 has and the time constant of the output resistance of the driver 7. The delay times from the cells 9 to the respective load cells 3 become the same because the channels 61, 62 are of the same form. Accordingly there exists no skew actually. |
