发明名称 VIDEO SIGNAL PROCESSOR
摘要 PURPOSE:To memorize the video signals equivalent to one picture screen after selection with every several scanning lines, at the same time reading out the video signals in a low speed to supply them to the low-speed input unit. CONSTITUTION:Output signal ES given from ITV unit 1 is written into 1-line speed conversion memory 3 through analog switch circuit 2. Signal ES read out of memory 3 in a low speed is supplied to the low-speed input unit after the A/D conversion. Vertical synchronous signal VD given from unit is counted by counter 7 featuring maximum 6 bits and then supplied to multiplexer 8. In the same way, horizontal synchronous signal HD is counted by counter 9 of maximum 6 bits and then decoded through decoder 10 to be supplied to multiplexer 8. Accordingly, multiplexer 8 is given to analog switch 2 plus control circuits 4 and 6 in the form of control signal RC which designates the scanning line of No.6N-5 (N=1, 2...). Thus the video signals equivalent to one picture screen can be supplied to the input unit with no loss.
申请公布号 JPS55121784(A) 申请公布日期 1980.09.19
申请号 JP19790028958 申请日期 1979.03.13
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 AOYANAGI KATSUHIKO;SUZUKI NOBUKAZU;NAGASHIMA SUMIO
分类号 H04N7/18;H04N7/12 主分类号 H04N7/18
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