| 摘要 |
<p>PURPOSE:To prevent malfunction by counting the horizontal synchronizing signal to detect the control word placed in the beginning of a data group only when the vertical synchronizing signal is obtained from an input signal. CONSTITUTION:When vertical synchronizing signal 14 is input to R-SFF17a, output 27 becomes high-level, and AND circuit 17b outputs horizontal synchronizing signal 16, and counter 17c counts this signal 16. Since output 28 of AND circuit 17d becomes high-level by the 6th horizontal synchronizing signal, which corresponds to the beginning of the control word, from the vertical synchronizing signal, AND circuit 19a outputs clock signal 30 which comes in the same cycle as data, and input data signal 22 is shifted because shift register 19b is clocked. Register 19b has 57 bits of contents discrimination signal 4, address signal 5 and control signal 6, and the last bit of signal 6 is 116th bit from synchronizing signal 2, and therefore, a control signal is assigned to all bits of register 19b when 116 signals 30 are input, thus preventing malfunction.</p> |
