| 摘要 |
PURPOSE:To make it secure to allot signals to subblocks by controlling a clock counter by detecting the block-synchronizing signal of the 1st subblock in one field of reproduced data. CONSTITUTION:This processor is equipped with circuit 50 that counts a clock from PLL321 on the basis of signal REV having a prescribed phase relation with the initial time point of the main block of reproduced data to generate 51 window pulse WP, outputs block-synchronizing signal BK of the 1st subblock as it is when it is within the width of WP, and obtains alternate pulse MP in the middle of the width of WP to obtain synchronizing signal PBK. Then, counter 61 is made to self- correlation to signal BK by the output CN1, and counter 62 is controlled by signals SR and PBK to restore absent signal BK by its outputs CN2 and PBK, eliminating influence of a mixed false pulse. |
