Low power and compact area digital integrator for a digital phase detector

摘要

In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

主权项

1. A circuit comprising:
a first circuit configured to receive a reference signal and a source signal and to generate a correction signal indicating a difference in phase between the reference signal and the source signal; a second circuit configured to receive the correction signal and to generate a digital signal indicating a phase-to-digital conversion of the correction signal; a third circuit configured to receive the digital signal and to generate a control signal indicating a converted value of the digital signal; a fourth circuit configured to receive the control signal and to generate a source signal in response to the control signal; and a fifth circuit configured to compare a characteristic of the digital signal to a predetermined range and to generate a lock signal if a characteristic of the digital signal indicates the ability to achieve phase-lock.