| 摘要 |
PURPOSE:To eliminate the jitter error of a digital output and at the same time increase both the accuracy and speed of conversion, by driving the FF circuits alternately with the double phase clock pulse and then giving a feedback so that a resetting is applied from a back stage to a front stage. CONSTITUTION:NAND gates Q01.Q02, Q11.Q12...Q41.Q42 plus Q14.Q15...Q44.Q45 form an R-SFF each, and these FFs are connected by connecting gates Q16, Q26... Q46. At the same time, the output of a gate Q11 is fed back to the input of Q01 with the output of Q21 to the input of Q11, and the similar feedbacks are carried out hereafter. Then the clock pulses phi and phi' having adverse phases to each other are applied to a terminal 108. Thus the shift pulse duration of each bit becomes equal to the clock pulse duration.The fall part overlaps the rise part of the next shift pulse for the output pulse trains of circuits Q12, Q22.... However, this overlap part can be eliminated by supplying the shift pulse to a latching circuit comprising Q13-Q15, Q23-Q24.... As a result, an equal pulse duration and equal generating interval of pulse can be obtained. |
