| 摘要 |
PURPOSE:To obtain a sample holding circuit which has a reduced amount of leakage of the sample holding pulse and can perform a high-speed operation with a small amount of power consumption, by controlling the supply of the input signal via a complementary transistor and at the same time controlling the sample holding to a capacitor with a high-input impedance element. CONSTITUTION:Complementary transistors 28A and 28B constituting a gate are switched via a pair of N type transistors 24A and 24B which receive the application of the contrary sample holding pulse at the base respectively. Then the supply of the input signal is controlled for a sample holding capacitor 29 connected with an FET30 of high input impedance. Thus the input signal and the sample holding pulse are transmitted through an unbalanced signal system and a balanced signal system respectively. At the same time, the leakage of the sample holding pulse is reduced by a high input impedance FET. Furthermore the dynamic range is increased owing to the use of the complementary transistors to realize a high-speed operation, and at the same time no current flows to the complementary transistors in the cut-off mode to reduce the power consumption. |
