| 摘要 |
PURPOSE:To achieve two-phase signal without overlap, by applying a basic clock to the 1st input terminal of two logical gates, and connecting each output terminal to the 2nd input terminal via a delay element. CONSTITUTION:When a basic clock phi0 rises to ''H'', the output of an NOR gate falls down to ''L'', and after it is delayed at an inverter, a clock -phi1 rises to ''H''. This is detected at an NAND gate and after delayed at INV3-INV5, a clock phi2 rises. Thus, the state of clocks phi1 and phi2 is changed by keeping time shift through inverters and no overlap is caused. On the other hand, the clock phi2 falls down to ''L'' and an NOR detects it, and the clock phi1 rises to ''H'' after delayed at inverters INV6, INV7. Thus, the clocks phi1, phi2 change while keeping time shift and no overlap is caused. |
