发明名称 PHASE LOCK LOOP
摘要 The invention provides an integrator (23) and a voltage controlled oscillator (12) to produce a variable frequency output signal (Vp min ). …<??>A primary loop (39) is locked to an input signal (VRec) and has a narrow bandwith allowing the output signal to precisely track the input signal. An initialization loop (41) is locked to an internally generated reference signal (VRef2) and has a wide bandwidth for pulling the frequency of the reference signal. A switch (22) selectively connects components of the primary loop (39) to the integrator (23) when the frequency difference between the reference signal and the outut signal is small and connects components of the initialization loop (41) to the integrator (23) when the frequency difference between the reference signal and the output signal is large.
申请公布号 JPS57106241(A) 申请公布日期 1982.07.02
申请号 JP19810173136 申请日期 1981.10.30
申请人 WESTINGHOUSE ELECTRIC CORP 发明人 RONARUDO ROIDO RII
分类号 H03L7/113;H03L7/10;H04L27/06 主分类号 H03L7/113
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