| 摘要 |
In the circuit, the latch circuit(L1)-(Ln) connected to each lead switch(S1) (Sn) is connected with the input of the encoder circuit(E) and the output of the encoder circuit(E) is connected to the memory medium through the output buffer circuit(B), and simultaneously, connected to the timing pulse generating circuit(C) through the OR circuit. The output of the latch circuit(L1) (Ln) is connected to the priority order circuit included in the input terminal side of the encoder circuit(E). The reset signal output(Re) of the timing pulse generating circuit(C) is connected to each latch circuit(L1)-(Ln).
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