| 摘要 |
PURPOSE:To realize a high-speed operation, by providing a parallel processing means which generates several kinds of data of the next instruction during the instruction execution. CONSTITUTION:An operation device group 2 consists esentially of subblocks 20, 40, and 60, and sublocks consist of adders 21, 41, and 61, subtractors 22, 42, and 62, mutipliers 23, 43, and 63, and dividers 24, 44, and 64 respectively. Latch circuit groups 10, 30, and 50 are installed in the input side of subblocks 20, 40, and 60 respectively. Every latch cirlcuit constituting latch circuit groups latches data on an input data bus 3 in accordance with a control signal on a control signal line 5 outputted from a system control device 1. All operation devices in each subblock are operated simultaneously except operation devices whose operation is not designated. Similarly, latch circuits are operated simultaneously except latch circuits whose operation is not designated. |
