| 摘要 |
The shift arithmetic debice,which can reduce the hardware size, includes a M-bit information register(1), a rotating type shifter(2), a logic '0' or '1' set cct. part(3), thememory devices(4-0,4-1) and an output register(6). The shifter(2) shifts the N-bit information by receiving the shift signals(SFT 1,SFT 2). The read only memory can be used as a memory device in the logic '0' or '1' set oct. part.
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