发明名称 VIDEO SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To obtain a video signal processing for a TV receiver capable of reduction in the number of external terminals and its cost. CONSTITUTION:A video processing circuit has a defeat control circuit 27 which is constituted that the operation of an automatic frequency tuning circuit 26 is stopped by applying a prescribed control voltage (VB) to a control input terminal 7 led outside an integrating circuit, a noise cancelling circuit 28 rejecting noise pulses in a video signal, and a lockout preventing circuit 31. The time constant of the said lockout preventing circuit is determined by connecting a capacitor C1 to the said control input terminal 7. Since the number 7 terminal of the integrated circuit is used to connect the capacitor determining the integration time constant of the said circuit 31 to a control input terminal of the said circuit 27, the number of external terminals of the integrated circuit is reduced.
申请公布号 JPS57159180(A) 申请公布日期 1982.10.01
申请号 JP19810044041 申请日期 1981.03.27
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 KADOKAWA SHIGERU;TONOMURA KENICHI
分类号 H04N5/213;H03J7/02;H04N5/50 主分类号 H04N5/213
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