| 摘要 |
PURPOSE:To improve an output falling time delay caused by a parasitic capacity, by using an emitter-follower transistor of a multiemitter structure, and applying its bias current to a transistor which is actively biased. CONSTITUTION:To an output of a current switching type logical circuit constituted of resistances R1, R2, transistors TRQ1, TRQ2 and a current source I1, an emitter-folower circuit consisting of an emitter-follower TRQ3 of a multiemitter structure, a parastic charge discharging pnp TRQ4, a diode D1 for constituting it bias circuit, and a resistance R3 is connected. In accordance with fall of an input, the base potential of the TRQ3 drops, and the base potential of the TRQ4 is scarcely delayed and drops, too. As a result, the output impedance of the TRQ4 drops, the charge of a parastic capacity Cs is discharged quickly, and after the discharge, a bias current value of the TRQ4 is returned to a stationary value again. Accordingly, a response in case of fall is quickened, a current is set to low impedance dynamically only in an instant of fall, and to high impedance in other case, therefore, low power consumption can be realized. |
