发明名称 BIT SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To stabilize bit synchronism to large variation of a transmitted signal, and to perform smooth phase follow-up operation for an extracted clock, by detecting the phase difference between the detected edge of a transmitted digital signal and a trigger pulse circulating in a shift register, and decreasing the phase difference. CONSTITUTION:A 1-0 transition edge of transmitted digital binary data is detected by an edge detecting circuit 3, and both a leading and a trailing edge output detected by the circuit 3 are applied as trigger signals to a timing control circuit 5. The output of this circuit 5 is inputted to a shift register circuit 4 receiving a basic clock. This circuit 4 is constituted as a flywheel circuit consisting of a shift register and a gate circuit. Then, the control circuit 5 detects the phase difference between the detected edge of the digital signal and a trigger pulse circulating the shift register to generate a timing signal so that the phase difference is reduced, and thus bit synchronism to large variation of the transmitted signal is stabilized to perform smooth phase follow-up operation for an extracted clock.</p>
申请公布号 JPS5868345(A) 申请公布日期 1983.04.23
申请号 JP19810166808 申请日期 1981.10.19
申请人 MATSUSHITA DENKI SANGYO KK 发明人 AKIYAMA TOSHIHIDE;SENOO TAKANORI;TAKEGUCHI YORIYASU;KOYAMA KENICHI
分类号 H04L7/027;H04L7/033 主分类号 H04L7/027
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