TFT LAYOUT STRUCTURE

摘要

A TFT layout structure comprising a first thin-film transistor (T1) and a second thin-film transistor (T2) controlled by a same control signal line. A first active layer (SC1) of the first thin-film transistor (T1) and a second active layer (SC2) of the second thin-film transistor (T2) are located at different layers and are spatially in a stacked arrangement. A first source (S1) and a first drain (D1) of the first thin-film transistor (T1) are in contact with the first active layer (SC1). A second source (S2) and a second drain (D2) of the second thin-film transistor (T2) are in contact with the second active layer (SC2). A bottom gate layer of the first thin-film transistor (T1) is arranged below the first active layer (SC1). A top gate layer of the second thin-film transistor (T2) is arranged above the second active layer (SC2). The TFT layout structure is capable of reducing the footprint of a circuit layout, increasing the flexibility of the circuit layout, and meeting requirements for a narrow edge frame and high resolution on a display panel.