发明名称 PICTURE SIGNAL PROCESSING CIRCUIT OF FACSIMILE
摘要 PURPOSE:To eliminate the inconvenience due to response delay, by delaying the output of a CCD image sensor by the response delay time of an automatic slice level control circuit. CONSTITUTION:A CCD analog processor 5, i.e., a delay element is inserted between a CCD image sensor 1 which reads th picture information out of an original and a picture signal amplifier 2 which amplifies the picture signal delivered from the sensor 1. The delay time (number of stages) of the processor 5 is selected in consideration of the response delay time of an automatic slice level control circuit 3. The output waveform of the amplifier 2 is delayed by the processor 5 and by a degree equivalent to the time corresponding to the response delay time of the circuit 3. This waveform is then applied to a comparator 4. As a result, the response delay due to the circuit 3 is cancelled.
申请公布号 JPS58175362(A) 申请公布日期 1983.10.14
申请号 JP19820057230 申请日期 1982.04.08
申请人 TOKYO SHIBAURA DENKI KK 发明人 YAMAMOTO TOSHIFUMI
分类号 H04N1/403;H04N1/40;(IPC1-7):04N1/40 主分类号 H04N1/403
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