发明名称 RESET SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To prevent a defect of a resetting due to ripples, noises, etc., by producing a reset signal when the time signal which increases in response to the time elapsed from application of a power supply and at the same time by lowering the level of the reference voltage. CONSTITUTION:The power supply voltage of an electronic device 2 of a microcomputer, etc. and the voltage of a terminal 13 of a Zener diode 12 rise up to the normal working voltage respectively when a fixed time elapses after application of a power supply. The charging voltage of a capacitor 3 exceeds the Zener voltage, i.e., the reference voltage with a slight time lag from the rise of the normal working voltage. Then the output of a comparator 11 is set at a high level, and a transistor 14 is turned on to reduce the level of the reference voltage. As a result, the output of the comparator 11 is kept at a high level even in case the charging voltage of the capacitor 3 is varied by the noises, etc. The output of the comparator 11 is applied to the device 2 as a reset signal via an inverter 10.
申请公布号 JPS58175321(A) 申请公布日期 1983.10.14
申请号 JP19820058486 申请日期 1982.04.08
申请人 FUJI XEROX KK 发明人 OOSUMI JIYUNICHI;HOSOKAWA HIDENORI
分类号 H03K3/02;H03K17/22 主分类号 H03K3/02
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