发明名称 DRIVING CIRCUIT OF CAPACITIVE LOAD
摘要 PURPOSE:To decrease the power consumption of an output resistor to a negligible extent and to improve high-frequency characteristics, by flowing only a current compensating the leakage of a capacitive load to an output resistor connected to a collector of a PNP transistor (TR) and an NPN TR. CONSTITUTION:An emitter of the PNP TRTR1 and the NPN TRTR2 is connected to an input signal terminal SIN via capacitors C1, C2, respectively. The collector of the TRTR1, TRTR2 is both connected to the capacitive load CL and the other end of the capacitive load CL is grounded. Further, the collector of the TRTR1 is connected to a power supply P120 via a resistor R1, the emitter is via a diode D1 and the base is via a resistor R3, respectively. Further, the base of the TRTR1 is grounded with a parallel circuit comprising a resistor R4 and a capacitor C2. Moreover, the capacitor C2 connected to the emitter of the TRTR2 is connected to a resistor R2 in parallel and the emitter is grounded via a parallel circuit comprising a capacitor C4 and a Zener diode ZD1, and the load CL is driven at high speed at a low power.
申请公布号 JPS58212225(A) 申请公布日期 1983.12.09
申请号 JP19820094913 申请日期 1982.06.04
申请人 HITACHI SEISAKUSHO KK 发明人 SHIRAISHI KIICHI
分类号 G09G1/00;H03K17/04;H03K17/66 主分类号 G09G1/00
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