| 摘要 |
PURPOSE:To manufacture the CMOSIC of a large latch-up resistance by making the surface concentration of a buried layer just under a section, to which a MOS transistor is not formed, higher than that of the buried layer just under a section to which the MOS transistor is formed. CONSTITUTION:The buried layer 19 is formed just under a P<-> type well 6, the impurity concentration of the surfaces of buried layer sections 20 just under P<+> isolations is made previously higher than that of the surface of the buried layer section 19 just under the source 3 and drain 4 regions of other sections, an N- MOSTB, and the floating of the buried layer sections 20 just under the P<+> isolations 9 is made larger than that of the buried layer section 19 of other sections. 21 Represents an N<-> type epitaxial layer. Accordingly, since a base region of a parasitic N-P-N transistor is formed by the buried layer of low concentration, hFE of the parasitic N-P-N transistor is lowered, and a latch-up can be prevented. |
