| 摘要 |
PURPOSE:To prevent the increase of the electrode resistance of a Schottky barrier gate FET having high integration by a method wherein a source electrode is arranged on the back surface of an N<+> type substrate, an N<-> layer on the upper surface, and drain electrodes via N layers, and then gate electrodes are provided at the groove bottom of the N layer between the drain electrodes. CONSTITUTION:The N layer 10, an operation layer 8, and the N layer 9 are laminated respectively approx. 2mum, 0.6mum, and 0.2mum on the N<+>-GaAs substrate 6, SiO2 masks 13 are applied, thus the grooves 14 reaching the substrate 6 are formed by etching. Next, selective epitaxial growing layer 15 are formed in the grooves 14 by using Ga organic compound, the drain electrodes 71 of Pt/AuGe are selectively formed, and then the source electrode 16 of AuGe is added to the back surface of the substrate. The grooves 17 are provided by etching between the drain electrodes, and the gate electrode 11 and the layer 72 of Au/Pt/Ti are formed by vapor deposition. Then, the substrate is formed into a fixed thickness by polishing the back surface together with the electrode 16 which is utilized for etching, AuGe is newly vapor-deposited and plated with Au, and thus the source electrode 2 is formed by heat treatment. Since the gate electrode can be formed without high temperature treatment in this manner, a desired device can be formed without the increase of electrode resistance. |
