| 摘要 |
PURPOSE:To prevent insulating breakdown at the time of applying a high voltage, shorten an access time and improve erasing efficiency by providing an erasing gate between the floating gate and control gate. CONSTITUTION:A polycrystalline silicon film is formed, phosphorus or arsenic is diffused into this film. Thereby, an erasing gate 27 which is the second conductive layer can be obtained through the photo etching. Thereafter, the second gate insulating film 28 is formed by the thermal oxidation method on the erasing gate 27. Moreover, the polycrystalline silicon film is formed by the CVD method thereon. Phosphorus or arsenic is diffused into such silicon film and a control gate 29 which is the third conductive layer can be obtained by the photo etching. Thereafter, the source 30 and drain 31 are formed by the selective diffusion of phosphorus or arsenic to the specified area of the semiconductor substrate 21. Next, after forming an insulating film 32 which covers the surface of the semiconductor substrate 22 providing a control gate 29 by the CVD method, the wiring 33 of the specified pattern is formed on the insulating layer 32 and it is connected to the drain 31 through a contact hole 34. Thereby, a semiconductor memory device 40 can be obtained. |
