发明名称 MAIN MEMORY OF CENTRAL PROCESSING UNIT WITH ALTERNATIVE MEMORY
摘要 PURPOSE:To replace a main memory without stopping a system even when the main memory is destroyed, by arranging two physical areas for the same logical area and switching them with a hardware circuit operated by a software instruction. CONSTITUTION:Logical addresses are given to the first main memory-1, 71, the second main memory-2, 73, and the third main memory-3, 75 in an ascending order. When the second main memory-2, 73 becomes abnormal, addresses of the second main memory-2, 73 are allocated to the second alternative memory-2, 74. When an address is sent from a processor to an address register 21, it is transmitted to a memory 11 and an alternative memory 12 through an address selecting line 42. With respect to stored contents accessed by a central processing unit, contents of the memory 11 are stored in a buffer device 23 if the value of a register 22 transmitted from a signal line 45 is 1, and contents of the memory 12 are stored in the buffer device 23 if this value is 0, and contents stored in the device 23 are transmitted to the central processing unit through a signal line 50. Thus, when the main memory is destroyed, the main memory is replaced partially or overall with respect to software and hardware without stopping the system.
申请公布号 JPS5942700(A) 申请公布日期 1984.03.09
申请号 JP19820152609 申请日期 1982.09.03
申请人 HITACHI SEISAKUSHO KK 发明人 OOHASHI HIDEHIRO
分类号 G06F12/16;G06F12/00;G11C29/00 主分类号 G06F12/16
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