发明名称 AUTOMATIC EQUALIZER
摘要 PURPOSE:To prevent the generation of nonlinear distortion by connecting plural integration circuits as delay elements of an equalizer in cascade to miniaturize the automatic equalizer and make the large-scale circuit integration easy. CONSTITUTION:Plural integration circuits 120 are connected in cascade to a signal input terminal IN of the automatic equalizer and the order of each integration circuit is brought to the 1st order of 1/S. Integration outputs P0t-Pkt of each circuit 120 are controlled by tap gain coefficients a0-ak, and the controlled signal is inputted to an adder 40. Each signal is added by the adder 40 and the result is inputted to an identification circuit 50 and an error signal detector 60. An identified output (gt) is outputted by the identification circuit 50 according to the result of addition, the error signal detector 60 dtects the difference between the identified output gt and an equalizing output (yt) to output a detecting error signal (et). Then, the automatic equalizer is miniaturized, the large-scale circuit integration is made easy, thereby preventing the generation of the nonlinear distortion.
申请公布号 JPS59135935(A) 申请公布日期 1984.08.04
申请号 JP19830009304 申请日期 1983.01.25
申请人 OKI DENKI KOGYO KK 发明人 IIDA MASAO;KOBAYASHI MASAKI
分类号 H03H21/00;H04B3/06;H04L25/03 主分类号 H03H21/00
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