| 摘要 |
PURPOSE:To form a delay element by a method wherein a resistor is provided on the current route of an inverter circuit. CONSTITUTION:The fundamental cell 3 such as LSI and the like has an CMOS structure which will be formed by an N type region 6 and a P type region 7. Polycrystalline silicon layers 8, 9 and 10 are formed on a substrate, the polycrystalline silicon layers 8 and 10 are used as a gate electrode and they form MOSFETs Q1, Q2, Q3 and Q4 together with the N type region 6 and the P type region 7. The drains of the MOSFETs Q1 and Q2 are connected common by a wiring 17, they constitute the first inverter 9, and their output is applied to the gate electrodes of the MOSFETs Q3 and Q4 which constitutes the second inverter through the intermediaries of the wiring 17, a wiring 18, the polycrystalline layer 9 and a wiring 19. As the resistance value of the polycrystalline silicon layer 9 is relatively high and it is inserted to the gate capacitance charging and discharging route of the second inverter as a resistor, the transfer of signals can be delayed. |
