发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To enable to obtain the withstand voltage of a bi-polar transistor to some degree without the inferiority of the characteristic of a J-FET to that of a discrete J-FET, by forming two epitaxial layers of different conductivity types on a substrate, and then forming the J-FET and bi-polar transistor on said layers. CONSTITUTION:A gate region 45, a drain region 52, a source region 53 and the J-FET having electrodes 55 for these regions are formed at the parts isolated by a P-epitaxial layer 44 and a P<+> one 47. Besides, a base region 49, an emitter region 50, a collector contact region 51 and the bi-polar transistor having electrodes for these regions are formed in the island region having an N-well region 45.
申请公布号 JPS59184559(A) 申请公布日期 1984.10.19
申请号 JP19830058867 申请日期 1983.04.04
申请人 NIPPON DENKI KK 发明人 KOBAYASHI DAISAKU
分类号 H01L29/808;H01L21/331;H01L21/337;H01L21/8222;H01L21/8248;H01L27/06;H01L29/73 主分类号 H01L29/808
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