发明名称 PLL SYNCHRONOUS DEMODULATING CIRCUIT
摘要 PURPOSE:To obtain a regenerated carrier which does not contain any of phase noises due to cross modulation by controlling the reference frequency oscillator of a PLL synchronous demodulating circuit by a DC component obtained from the difference signal between an input signal to be demodulated and an orthogonal demodulation output. CONSTITUTION:The input signal to be demodulated is passed through a switching circuit 11, limiter circuit 12, and LPF13 to demodulate a sum signal component. Further, the signal passed through the circuit 12 and a BPF23 is switched by a switching circuit 15 by an in-phase demodulated carrier obtained through the PLL synchronous demodulating circuit 14 to obtain a subtraction component for the difference signal through an LPF16. The orthogonal demodulation output obtained through a switching circuit 17 and an LPF18 included in the circuit 14 is divided 19 by the output of the LPF16 to obtain the difference signal. This difference signal is passed through the loop filter 20 of the circuit 14 to obtain a DC component, by which the reference frequency oscillator 21 of the circuit 14 is controlled to obtain the regenerated carrier which does not contains any of phase noises of cross modulation low frequency between the sum signal and difference signal.
申请公布号 JPS59204320(A) 申请公布日期 1984.11.19
申请号 JP19830078458 申请日期 1983.05.04
申请人 TOSHIBA KK 发明人 HIRAYAMA KOUICHI
分类号 H04B1/16;H03D1/22;H04H40/45 主分类号 H04B1/16
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