| 摘要 |
PURPOSE:To equalize the capacitances due to diffused layers parasitic to a pair of data lines in the relation of complementary elements connected to an MOS transistor for column selecting line by a method wherein the title device consists of such a layout that the total area of the diffused layers to form the source of said transistor belonging to a pair of data lines. CONSTITUTION:The diffused layers C1'-C3', C1'-C3' are to form the source of said transistor. This device has such a layout that the layers C1'-C3' are connected to the data line D, and the layers C1'-C3' to the data line D. That is, in this layout, the sizes of the diffused layers connected to a pair of data lines in the relation of complementary elements are equal without the difference in size of the layers connected to the lines in such a relation as conventional, and then the jnnction capacitance of data lines becomes equal. |
