| 摘要 |
PURPOSE:To decrease the number of constituent transistors (TR) and realize the fast propagation of a signal by activating complementarily a transfer gate and a tri-state inverter, and outputting NOR outputs as they are and inverting and outputting NAND outputs respectively. CONSTITUTION:This decoder circuit is equipped with a NOR gate which inputs two input signals, a NAND gate which inputs said two input signals, the transfer gate 7 which inputs the output of the NOR gate, and the tri-state inverter 8 which inputs the output of the NAND gate and have its output connected to the output of the transfer gate 7 in common. This transfer gate 7 and tri-state inverter 8 are activated complementarily according to the logical level of the 3rd input signal. Consequently, 28 TRs which are necessary before are reduced to 22 TRs, the rapid propagation of the signal is achieved, and the ability to drive signal lines is made high. |
