发明名称 SIGNAL RECEPTION CIRCUIT
摘要 PURPOSE:To prevent malfunction and to attain reduction of time for inservice processing by inhibiting the signal reception at the transient state of state transition of a call processing section in a digital signal processing circuit of an exchange. CONSTITUTION:A 2-input OR gate 12 and a selector 13 to write a low level at inactivating are added. Thus, a last look memory 7 is not revised at write to a hard Q memory 5 and the write of an identical signal from the (N+3)th frame and succeeding frames is suppressed by the write of an active memory 8. Moreover, a processing section reads this signal and performs the revision of the last look memory 7 and activation of the active memory 8 at the state transition. The in-service processing for duplicated running is realized by a simultaneous write order of the last look memory 7 and the active memory 8 from the call processing section.
申请公布号 JPS6074795(A) 申请公布日期 1985.04.27
申请号 JP19830180698 申请日期 1983.09.30
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA;HITACHI SEISAKUSHO KK 发明人 SHIMOE TOSHIO;TAKAHASHI TATSUROU;ARAGAKI NAOYA;GOUHARA SHINOBU
分类号 H04Q1/20;H04M3/24 主分类号 H04Q1/20
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