| 摘要 |
<p>PURPOSE:To make it possible to apply a clock skew test to a logical operation circuit having a plurality of hold circuits operated by a same phase clock, by supplying a clock with predetermined phase difference to first and second signal holding means. CONSTITUTION:In fundamental operation, a fundamental clock 9 is selected and applied as clocks 10, 11 and an information signal 5 is set to a register 1 while an information signal 6 being the output thereof is applied to a combination logical circuit 2. Thereafter, the signal 6 is subjected to determined logical operation to be set to a register 3 as an information signal 7 while an information signal 8 is outputted from an output terminal 8'. On the other hand, in test operation, the clock 9, a delay clock 24 or a delay clock 28 and the clock 9 are selected in selector circuits 20, 21 on the basis of selection signals 25, 26. If normal operation is performed in this test operation, in a standard state, it can be confirmed that there is a operative surplus due to change in a temp. or voltage.</p> |
