发明名称 PLL CIRCUIT
摘要 PURPOSE:To attain extraction of a high frequency rectangular wave signal by making an edge number of both rectangular wave signals coincident with each other in obtaining the 2nd rectangular wave signal having a constant inverted period phase-locked to the 1st rectangular wave signal whose inverting period is not constant. CONSTITUTION:A BPM modulation signal fed to a terminal 1 is inputted to an edge detecting circuit comprising a delay circuit 20 and an EXOR circuit 21. An edge addition circuit comprising a delay circuit 22 and an OR circuit 23 arranges forcibly the edge number of an edge detecting signal (b) to the edge number of an output signal of a voltage controlled oscillator VCO11. An FF comprising NAND circuits 26, 27 detects the phase lag of an output signal (d) of the OR circuit 23 by comparing the trailing edges. Furthermore, an FF comprising NAND circuits 28, 29 detects the phase lead of the signal (d) by comparing leading edges. Detecting signals (f), (g) control the VCO11 via a charge pump 8, an LPF9 and an amplifier 10.
申请公布号 JPS60123135(A) 申请公布日期 1985.07.01
申请号 JP19830231671 申请日期 1983.12.07
申请人 CANON KK 发明人 MASUI TOSHIYUKI;HIRASAWA KATAHIDE;KOUZUKI SUSUMU;KASHIDA MOTOICHI;TAKEI MASAHIRO
分类号 H03L7/08;H03L7/089;H04L7/033 主分类号 H03L7/08
代理机构 代理人
主权项
地址