| 摘要 |
PURPOSE:To pull-in quickly an oscillation frequency to a normal value by generating continuously an error signal generated based on an output signal from a frequency comparing circuit until an oscillation frequency of a voltage controlled oscillator in a phas locked loop attains the normal value. CONSTITUTION:An EFM signal of an input terminal 1 is supplied to a detecting window pulse generating circuit DWC and a frequency comparing circuit FCC. In the FCC, the pulse width of a pair of pulses PSP, PSE constituting a synchronizing signal Ps of the EFM signal is counted by a bit clock signal Pc obtained from a voltage control oscillator VCO, and in case count values have exceeded N, respectively, a signal S1 is generated, and when there is no error, said value gors to N. In case a total value exceeds (2N+1), a signal S2 is generated. In error signal generating circuits ESG1, ESG2, error signals S1e, S2e are outputted by the signals S1, S2, respectively, the error signal of a phase comparing circuit PC is controlled by the error signals S1e, S2e supplied to a terminal 12, and a phase locked loop PLL is set quickly to phase locked state. |
