| 摘要 |
PURPOSE:To make it unnecessary to invert a read/write line in an input/output side by constituting a titled system so that a DMA controller informs to a memory that it is in a DMA transfer mode, and it is operated by converting the data read informed by the read/write line of a common bus to the write. CONSTITUTION:When a DMA controller DMAC obtains a bus control right from a central processor CPU and a data transfer is executed by a DMA mode between a memory MEM and input/output devices I/O1, I/O2, an R/W signal for determining its direction is made to coincide with the R/W direction of the input/output device, and the MEM inverts it. The DMAC informs that it is in a DMA mode, to the MEM through a control line CLo, and makes a response to H and L of an R/W line opposite to that of the time of access to the CPU, namely, a data is inputted and written if the R/W line is H, and the data is sent out and read out if said line is L. The input/output device side is the same at the CPU access time and not changed, and the data is sent out and read out if the R/W line is H, and the data is inputted and written if said line is L. |
