SEMICONDUCTOR STORAGE DEVICE

摘要

PURPOSE:To perform high-speed operation by timing the charging and discharging of an address and a data line with the same signal. CONSTITUTION:Input part data lines D'I1-D'IM are selected by a decoder 10 which decodes an address signal 60. The operation of this decoder 10 is controlled with the output of the inverter of a P channel MOS transistor Q''001 and an N channel MOS transistor Q''002 connected between a power source VDD and the ground, and the operation of this inverter is controlled with an input signal supplied to an input terminal 30. Then, P channel MOS transistors Q''01... Q''0M, and Q''101...Q''10N are supplied with a single input signal from an input terminal 30 to control the precharge of the address line and data line.