发明名称 MOS STATIC RAM
摘要 PURPOSE:To attain high speed operation and low power consumption by providing a variable load means controlled so as to increase the impedance at write in comparison with at read or chip non-selecting state. CONSTITUTION:A write circuit WA controls the operation with a control signal phiw and outputs a complementary data signal corresponding to an input data fed to a data input terminal Din in the operating state to common complementary lines CD, CD'. The write circuit WA brings a couple of output terminals to a high impedance state or a floating state in the non-operating state. At write, a high level and a low level are fed to the selected complementary data line from the write circuit WA, and the low level on the data line is brought a lower potential by increasing the impedance of a load circuit so as to speed up the write. A reactive current is annihilated and the lower power consumption is attained.
申请公布号 JPS60258791(A) 申请公布日期 1985.12.20
申请号 JP19840113001 申请日期 1984.06.04
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 YAMAMOTO AKIRA;MINATO OSAMU;SAEKI AKIRA;YOSHITOMI YASUO;NAKAMURA HIDEAKI;KUBODERA MASAAKI
分类号 G11C11/417;G11C11/34;G11C11/419 主分类号 G11C11/417
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