发明名称 TEST COVERAGE SYSTEM FOR LOGICAL SIMULATION
摘要 PURPOSE:To improve the efficiency of logical simulation by replacing the working frequency of a specific memory means and the passing frequency through said memory means based on the signal changing information for each signal identification name of a logical circuit and the passing information for each bus identification between steps. CONSTITUTION:A coverage check information file 8 is produced with a microprogram source code file 5 and a signal information file 6 and by a coverage check information production processing 1. The file 8 contains a file which stores a correspondence table between the signal identification names of a logical circuit and the working frequencies of these names and a file which stores a correspondence table between the inter-bus identifications of a microprogram and their passing frequencies. Then a trace information file 9 is produced from a file 7, i.e., the result of a logical simulation 12 through a simulation result information analysis processing 2. Both files 8 and 9 are collated with each other through an information replacement processing 3, and the file 8 is replacement.
申请公布号 JPS61127042(A) 申请公布日期 1986.06.14
申请号 JP19840248111 申请日期 1984.11.26
申请人 HITACHI LTD 发明人 KATO ZENTARO;FUKUOKA KOHEI;KUBO KANJI;KONDO KUNIAKI;NAKAGAWA KOICHI;WAKAI KATSURO
分类号 G06F11/25;G06F9/22;G06F11/26;G06F11/28;G06F17/50 主分类号 G06F11/25
代理机构 代理人
主权项
地址