| 摘要 |
PURPOSE:To grasp quantitatively the debugging situation by registering the execution situation of a microprogram in a memory circuit and observing the registered result. CONSTITUTION:The titled processor is constituted of a control memory 1, a microprogram read register 2, a microprogram address register 3, a microprogram address generating circuit 4, a write data generating circuit 5 and a memory circuit 6. Address information stored in the address register 3 is inputted to the control memory 1, and one word in microprogram language in the memory 1 is set to the read register 2. In order to generate an address to be executed next, contents in a field 21, which express the internal branch command in the read register 1, and those in a field 22, which express address information to be executed next, are transmitted to the address generating circuit 4, and the address is decided. Moreover in terms of write data in the memory circuit 6 only an output 1 in the generating circuit 5 is actually made '0', and a step can be discriminated to be valuation or non-valuation. |
