MEMORY CONTROLLER WITH INTERLEAVED QUEUING APPARATUS

摘要

Memory controller appts. for processing number of memory requests has several queue circuits having address, control and data queue registers and tri-state flip/flop for independent operation. The device also includes the control circuits which divide the operating cycle selectively when the control register stores memory requests processed with control queue. The device provides the parallel operation for the memory requests by interleaving the different types of memory requests. And the device reduces the normal delay by parallel processing.