| 摘要 |
PURPOSE:To achieve an easy and accurate processing with such an arrangement that an error time is memorized into a data latch circuit by the first operation of a pass control switch and a newly calculated error time is added to a memorized value of the latch circuit by the second operation of the switch. CONSTITUTION:When a pass control switch 1 is turend on, an output Q is transmitted to data latch circuits 8, 13 and 22 by way of an inverter 3 and a D type FF4. The circuit 8 latches and transmits a running range of a triple counter 7 to an indicator 9. The circuit 13 makes the output of a clock counter 12 indicated on an indicator 14. The circuit 22 has an error time displaying 25. The output Q of the FF4 clears a memory 17. A designated speed is set by a switch 2. When the switch 1 is turned on, the latching of the latch circuits 8, 13 and 22 is released. A new error time is added to the value of the circuit 22 through dividers 18 and 20 and a subtractor 21 and transmitted to a display 25 through a converter 23 ane a decoder driver 24. This enables an easy and accurate pass control processing. |
